1. Field of the Invention
This invention relates generally to digital logic circuitry, and particularly to a scannable limited switch dynamic logic (LSDL) circuit.
2. Description of Background
Digital logic circuitry is used for many purposes, particularly, for example, in computer devices. With such extensive usage, the ability to routinely test digital logic circuits for proper operation is desirable, for example, when initially testing newly fabricated digital logic circuitry or when powering up or operating a device that includes this circuitry, such as a computer. Designing so-called “scannable” circuits is an example of a popular technique to provide such routine testing capability. In scannable digital logic circuits, additional circuitry is included to ensure the typical operation of the circuit is free of malfunctions, for example, prior to the normal operation of the circuit.
Limited switch dynamic logic (LSDL) is a hybrid combination of static logic circuitry (e.g., non-time-varying or sequential circuits, such as a so-called “latch” circuit) and dynamic logic circuitry (e.g., time-varying or “clocked” circuits, such as a so-called “domino” circuit). Thus, a basic LSDL circuit includes the combination of a latch circuit and a domino circuit. LSDL circuits offer desirable characteristics when used for digital logic circuitry, such as fast operation and low power consumption. However, scannable LSDL circuit designs can result in undesired impacts on these characteristics and, therefore, scannable LSDL circuit designs that maintain these beneficial characteristics are desirable.